1. Field of the Invention
The present invention relates to an embedded capacitor fabrication and, more particularly, to a method for forming a metal-insulator-metal capacitor in logic circuit.
2. Description of the Prior Art
In the field of integrated circuits, it is preferable to form circuit elements in the smallest achievable surface area in order to realize a high degree of circuit complexity into a small integrated circuit chip size, resulting in low cost per function. The mixed-mode process can provide a process flow with embedded capacitor in logic circuit. The addition of a capacitor can be used for an RC analog circuit or other special applications
Referring to FIG. 1, a metal-oxide-semiconductor field effect transistor having a gate 14C, gate oxide 14D, drain 14B and source 14A is formed in and on a substrate 10. Further, a bottom electrode 20 of capacitor is formed on a field oxide region 12. Dielectric layer 21 and top electrode 22 are formed in sequence. Then, after interlevel dielectric layer 30 is formed on the semiconductor device, contact 32 is formed in the interlevel dielectric layer 30.
For a conventional mixed-mode process, the material of top electrode 22 and bottom electrode 20 is polysilicon. However, the polysilicon depletion will cause the different capacitance values under different bias voltage, as shown in FIG. 2.